? semiconductor components industries, llc, 2002 february, 2002 rev. 1 1 publication order number: nbsg11/d nbsg11 2.5v/3.3vsige 1:2 differential clock driver with rsecl* outputs *reduced swing ecl the sg11 is a silicon germanium 1to2 differential fanout buffer, optimized for low skew and ultralow jitter. inputs incorporate internal 50 termination resistors and accept necl (negative ecl), pecl (positive ecl), cml, or lvds. outputs are rsecl (reduced swing ecl), 400 mv. ? maximum input clock frequency > 12 ghz typical ? 30 ps typical rise and fall times ? 125 ps typical propagation delay ? rspecl output with operating range: v cc = 2.375 v to 3.465 v with v ee = 0 v ? rsnecl output with rsnecl or necl inputs with operating range: v cc = 0 v with v ee = 2.375 v to 3.465 v ? rsecl output level (400 mv peaktopeak output), differential output only ? 50 internal input termination resistors ? compatible with existing 2.5 v/3.3 v lvep, ep, and lvel devices http://onsemi.com l = wafer lot y = year w = work week *for further details, refer to application note and8002/d fcbga16 ba suffix case 489 marking diagram* sg 11 device package shipping ordering information nbsg11ba 4x4 mm fcbga16 100 units/tray nbsg11bar2 4x4 mm fcbga16 500/tape & reel lyw board description sg11evb nbsg11ba evaluation board
nbsg11 http://onsemi.com 2 vtclk, vtclk 50 * pin will default low when left open. ** pin will default to a slightly higher potential than clk when both are left open. figure 1. pinout (top view) vtclk clk clk v ee vtclk nc v ee nc nc q1 v cc v cc nc q0 q0 q1 a b c d 12 34 50 (a1) vtclk (b1) clk (c1) clk (d1) vtclk v ee (b2, c2) v cc (b3, c3) figure 2. logic diagram 75 k 75 k 36.5 k q1 (a4) q1 (b4) q0 (c4) q0 (d4) pin description pin clk*, clk ** q0, q0 q1, q1 rsecl data outputs function ecl, ttl, cmos, cml, lvds compatible (clk) inputs v cc positive supply v ee negative supply 50 internal input termination resistor nc no connect interfacing options connections cml connect vtclk and vtclk to v cc lvds connect vtclk and vtclk together accoupled bias vtclk and vtclk inputs within (vihcmr) common mode range rsecl, pecl, necl standard ecl termination techniques
nbsg11 http://onsemi.com 3 attributes characteristics value internal input pulldown resistor (clk, clk ) 75 k w internal input pullup resistor (clk ) 36.5 k w esd protection human body model machine model > 2 kv > 100 v moisture sensitivity (note 1) level 3 flammability rating ul 94 v0 @ 0.125 oxygen index 28 to 34 transistor count 125 meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d. maximum ratings (note 2) symbol parameter condition 1 condition 2 rating units v cc positive power supply v ee = 0 v 3.6 v v ee negative power supply v cc = 0 v 3.6 v v i positive input v ee = 0 v v i v cc 3.6 v v i positive in ut negative input v ee = 0 v v cc = 0 v v i ? ?? ? ? v ee 3 . 6 3.6 v v i out output current continuous surge 25 50 ma ma ta operating temperature range 40 to +70 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junctiontoambient) (note 3) 0 lfpm 500 lfpm 16 fcbga 16 fcbga 108 86 c/w c/w q jc thermal resistance (junctiontocase) 1s2p (note 3) 16 fcbga 5 c/w t sol wave solder < 15 seconds 225 c 2. maximum ratings are those values beyond which device damage may occur. 3. jedec standard multilayer board 1s2p (1 signal, 2 power).
nbsg11 http://onsemi.com 4 dc characteristics, input with rspecl output v cc = 2.5 v; v ee = 0 v (note 4) 40 c 25 c 70 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 45 60 75 45 60 75 45 60 75 ma v oh output high voltage (note 5) 1450 1530 1575 1525 1565 1600 1550 1590 1625 mv v outpp output pp voltage 350 410 525 350 410 525 350 410 525 mv v ih input high voltage (singleended) (note 7) v cc 1435 mv v cc 1000 mv* v cc v cc 1435 mv v cc 1000 mv* v cc v cc 1435 mv v cc 1000 mv* v cc v v il input low voltage (singleended) (note 8) v ih 2.5 v v cc 1400 mv* v ih 150 mv v ih 2.5 v v cc 1400 mv* v ih 150 mv v ih 2.5 v v cc 1400 mv* v ih 150 mv v v ihcmr input high voltage common mode range (differential) (note 6) 1.2 2.5 1.2 2.5 1.2 2.5 v r t internal termination resistor 45 50 55 45 50 55 45 50 55 w i ih input high current (@ v ih , v ihmax ) 30 100 30 100 30 100 m a i il input low current (@ v il , v ilmin ) 25 100 25 100 25 100 m a note: sige circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been estab lished. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 4. input and output parameters vary 1:1 with v cc . v ee can vary +0.125 v to 0.965 v. 5. all loading with 50 w to v cc 2.0 volts. v oh /v ol measured at v ih /v il . 6. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 7. v ih cannot exceed v cc . 8. v il always v ee . *typicals used for testing purposes. dc characteristics, input with rspecl output v cc = 3.3 v; v ee = 0 v (note 9) 40 c 25 c 70 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 45 60 75 45 60 75 45 60 75 ma v oh output high voltage (note 10) 2250 2330 2375 2325 2365 2400 2350 2390 2425 mv v outpp output pp voltage 350 410 525 350 410 525 350 410 525 mv v ih input high voltage (singleended) (note 12) v cc 1435 mv v cc 1000 mv* v cc v cc 1435 mv v cc 1000 mv* v cc v cc 1435 mv v cc 1000 mv* v cc v v il input low voltage (singleended) (note 13) v ih 2.5 v v cc 1400 mv* v ih 150 mv v ih 2.5 v v cc 1400 mv* v ih 150 mv v ih 2.5 v v cc 1400 mv* v ih 150 mv v v ihcmr input high voltage common mode range (differential) (note 11) 1.2 3.3 1.2 3.3 1.2 3.3 v r t internal termination resistor 45 50 55 45 50 55 45 50 55 w i ih input high current (@ v ih , v ihmax ) 30 100 30 100 30 100 m a i il input low current (@ v il , v ilmin ) 25 100 25 100 25 100 m a note: sige circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been estab lished. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 9. input and output parameters vary 1:1 with v cc . v ee can vary +0.925 v to 0.165 v. 10. all loading with 50 w to v cc 2.0 volts. v oh /v ol measured at v ih /v il . 11. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 12. v ih cannot exceed v cc . 13. v il always v ee . *typicals used for testing purposes.
nbsg11 http://onsemi.com 5 dc characteristics, necl or rsnecl input with necl output v cc = 0 v; v ee = 3.465 v to 2.375 v (note 14) 40 c 25 c 70 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 45 60 75 45 60 75 45 60 75 ma v oh output high voltage (note 15) 1050 970 925 975 935 900 950 910 875 mv v outpp output pp voltage 350 410 525 350 410 525 350 410 525 mv v ih input high voltage (singleended) (note 17) v cc 1435 mv v cc 1000 mv* v cc v cc 1435 mv v cc 1000 mv* v cc v cc 1435 mv v cc 1000 mv* v cc v v il input low voltage (singleended) (note 18) v ih 2.5 v v cc 1400 mv* v ih 150 mv v ih 2.5 v v cc 1400 mv* v ih 150 mv v ih 2.5 v v cc 1400 mv* v ih 150 mv v v ihcmr input high voltage common mode range (differential) (note 16) v ee +1.2 0.0 v ee +1.2 0.0 v ee +1.2 0.0 v i ih input high current (@ v ih , v ihmax ) 30 100 30 100 30 100 m a i il input low current (@ v il , v ilmin ) 25 100 25 100 25 100 m a note: sige circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been estab lished. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 14. input and output parameters vary 1:1 with v cc . 15. all loading with 50 w to v cc 2.0 volts. v oh /v ol measured at v ih /v il . 16. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 17. v ih cannot exceed v cc . 18. v il always v ee . *typicals used for testing purposes. ac characteristics v cc = 0 v; v ee = 3.465 v to 2.375 v or v cc = 2.375 v to 3.465 v; v ee = 0 v 40 c 25 c 70 c symbol characteristic min typ max min typ max min typ max unit f max maximum frequency (see figure 3. f max /jitter) (note 19) 10.709 > 12 10.709 > 12 10.709 > 12 ghz t plh , t phl propagation delay to output differential 90 125 160 90 125 160 90 125 160 ps t skew duty cycle skew (note 20) withindevice skew (note 21) devicetodevice skew (note 22) 3 6 25 15 15 50 3 6 25 15 15 50 3 6 25 15 15 50 ps t jitter cycletocycle jitter (rms) (see figure 3. f max /jitter) (note 19) 0.5 1 0.5 1 0.5 1 ps v inpp input voltage swing/sensitivity (differential) (note 23) 75 2600 75 2600 75 2600 mv t r t f output rise/fall times q, q (20% 80%) 20 30 55 20 30 55 20 30 55 ps 19. measured using a 500 mv source, 50% duty cycle clock source. all loading with 50 w to v cc 2.0 v. for minimum f max value of 10.709 ghz, output amplitude is approximately 200 mv (as shown in figure 3, where output pp spec is shown as a minimum/guarantee of around 150 mv). 20. see figure 4. t skew = |t plh t phl | for a nominal 50% differential clock input waveform. 21. withindevice skew is defined as identical transitions on similar paths through a device. 22. devicetodevice skew for identical transitions at identical v cc levels. 23. v inpp (max) cannot exceed v cc v ee .
nbsg11 http://onsemi.com 6 ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ??? ??? ??? ??? ??? ??? ??? ??? ?? ?? ?? ?? ?? ?? ?? ?? ??? ??? ??? ??? ??? ??? ?? ?? ?? ?? ??? ??? ??? ??? 0 100 200 300 400 500 600 123456789101112 frequency (ghz) 0.5 0.5 1.5 2.5 3.5 4.5 5.5 6.5 7.5 8.5 9.5 figure 3. f max /jitter v outpp (mv) jitterout ps (rms) output amp. ?????? ?????? output pp spec ????? rms jitter t phl figure 4. ac reference measurement clk clk q q t plh v pp receiver device driver device q q d d 50 w 50 w v tt figure 5. typical termination for output driver and device evaluation (refer to application note and8020 termination of ecl logic devices) v tt = v cc 2.0 v
nbsg11 http://onsemi.com 7 package dimensions fcbga16 ba suffix plastic 4x4 (mm) bga flip chip package case 48901 issue o 0.20 laser mark for pin 1 identification in this area d e m a1 a2 a 0.10 z 0.15 z rotated 90 clockwise detail k 5 view mm e 3 x s m x 0.15 y z 0.08 z 3 b 16 x feducial for pin a1 identification in this area 4321 a b c d 4 16 x notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimension b is measured at the maximum solder ball diameter, parallel to datum plane z. 4. datum z (seating plane) is defined by the spherical crowns of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package. dim min max millimeters a 1.40 max a1 0.25 0.35 a2 1.20 ref b 0.30 0.50 d 4.00 bsc e 4.00 bsc e 1.00 bsc s 0.50 bsc k x y m m z
nbsg11 http://onsemi.com 8 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. nbsg11/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada
|
